As transistor density has been increasing, power density has also been increasing. Thermal design and thermal packaging are sometimes designed such that when all components are run at maximum frequency and worst case power conditions, thermal design limits may be exceeded. This has previously been addressed by monitoring temperature and power consumption, and then actuating throttling mechanisms to reduce temperature or power consumption when conditions were approaching or exceeding thermal design limits.
Throttling typically takes the form of reducing frequency, which unfortunately reduces performance as well. However, reducing frequency uniformly runs the risk of applying this power reduction technique throughout the system, even in areas where it is not needed, and thereby reducing the performance of all areas. Past attempts at applying frequency reduction non-uniformly have typically been based on criteria such as the power efficiency of different elements. None of these approaches addresses the goal of keeping the most important functions running at high speed.